In DDR1 and DDR2 data bus systems used, for example, in PCs, servers, workstations, notebooks, and the like, bidirectional buses are used for data transmission. In this context, for example, eight data lines are routed in parallel from a controller to the DRAM (Dynamic Random Access Memory). The “DQ (Data Queue) signals” carried on these lines are synchronized to a “DQS (Data Queue Strobe) signal” carried on a further line, which is parallel to the data lines for the DQ signals. This DQS signal is transmitted in sync with the source, i.e., in the same direction as the DQ signals. If neither write access nor read access is taking place on the bus, the signals are in a “high impedance mode,” i.e., the lines are driven or terminated neither by the DRAM nor by the controller. The signals lock onto a “tristate level,” i.e., a level situated between the range of a definite 1 level (high level) and the range of a definite 0 level (low level). In this case, the DQS signal may encounter a special case.
The DQS signaling in data bus systems based on the DDR2 specification can be operated in differential fashion. In this context, two DQS signals are used, namely a DQS signal and a /DQS signal, which is the inverse of the DQS signal. During the actual data transmission operation, the DQS signals change their respective state from a high level to a low level and vice-versa at the clock frequency specified by a clock generator signal. In this case, the respective crossing of the DQS signals, i.e., the zero crossing of the differential signal DQS−/DQS, determines the timing of the data transmission operation. In particular, crossing of the DQS signals denotes a time at which the data signals transmitted on the DQ lines reach their intended state and should have met any “setup and hold conditions.”
This mode of operation is also preferred at clock frequencies above that of the DDR2-667 standard due to advantages of the differential signaling. A difficulty in this case is that a DRAM receiver needs to recognize when the preamble is driven on the bus. The preamble is the period after the DQS signal has left the tristate and is held at a low level up to the first data transmission, while the /DQS signal by definition likewise leaves the tristate and is held at a high level up to the first data transmission.
The DRAM specification allows a relatively large range in which the preamble needs to start (clock edge ±0.25 tck) and specifies only a very short preamble time (0.35 tck). For a DRAM connected to the bus, for example, these time-critical specification presets mean that it is very difficult to recognize that the DQS signal is definitively no longer in tristate, i.e., that the preamble has been initiated, and that the next DQS edge therefore needs to be used to determine the data transmission timing. Specifically in the case of DDR3 with data rates of up to 1.6 Gb/s per pin and bit times of 625 ps, conventional methods of recognizing the first data correctly are difficult or even impossible to implement.
One possible solution to this problem of the DQS signal was that the controller disconnects the DQS signal only during reading, and accordingly always keeps the DQS and /DQS signals at a defined level. This consumes an unnecessary amount of power, however, and therefore does not represent a satisfactory solution. Similarly, various complex receiver implementations exist that recognize a correspondingly short preamble. Besides their complexity, however, these also have other associated drawbacks, such as increased input capacity, which impairs the signal integrity of the input signals at high data rates.
FIG. 3 shows a conventional data bus system 300 based on the DDR2 specification in schematic form that includes a controller 301 and a DRAM 302 connected to one another by a bidirectional DQ line 311 for data transmission. To synchronize the data transmission, the controller 301 and the DRAM 302 are additionally connected to one another by a bidirectional DQS line 312 and a bidirectional /DQS line 313 for interchanging differential DQS signals. Both the controller 301 and the DRAM 302 have terminations 321 and transmission and reception amplifiers 322, which are respectively connected to an appropriate end of one of the aforementioned lines. The terminations 321 include two resistors configured as voltage dividers. The resistors normally each having a resistance value around 120. Resistance values around 100 Ω, 150 Ω or 300 Ω are likewise usual.
During a write operation, i.e., during data transmission via the bus, the termination 321 is first turned on before the transmission amplifier 322 (denoted as controller driver) in the controller 301 drives the associated line to a high or low level. The termination 321 helps to prevent reflections. The termination 321 means that at the start of a write operation both DQS and /DQS have a midlevel signal level situated between the supply voltage VDD and the common grounding system VSS, i.e., at (VDD+VSS)/2. As described above, the driving of the DQS line 312 to a zero level up to the first genuine (i.e., data-transmitting) edge is called the preamble. The write operation then takes place. After the last written bit, a postamble for the DQS occurs. After that, the driver 322 on the controller 301 disconnects. Only then is the termination 321 disconnected, which ensures that the DQS and /DQS lines 312, 313 are respectively pulled back to the midlevel signal level.
The procedure described above is shown graphically in schematic form in FIG. 4. The figure shows the profiles of a clock generator signal labeled clock signal, a command signal labeled CMD signal, a DQS signal drawn in solid lines, a /DQS signal drawn in dashed lines, and a DQ signal.
The DQS and /DQS signals are at the midlevel signal level before the write operation. As preamble, the DQS signal is driven to a low level and the /DQS signal is driven to a high level. Changes to the state of the DQS signal or of the /DQS signal, which follow the preamble determine the timing of the data transmission taking place with the DQ signal, as described above. Following the data transmission, the DQS and /DQS signals return to the midlevel signal level.